| >As ChipsAndCheese points out, the uArch diagrams of modern high-performance ARM and x86 cores look very similar. So far so good. >And the real answer, is that both designs are neither RISC or CISC This is... Not even wrong. >(the fact that one implements a CISC-derived ISA and the other implements a RISC-like ISA is irrelevant to the actual microarchtecture). Exactly. CISC and RISC are characteristics of the ISA, not the microarchitecture. But note (and I can't stress this enough), this does not mean ISA doesn't matter. The ISA is the interface between software and hardware. A well designed ISA will e.g.: - Not restrict the actual design of the microarchitecture. - Not expose microarchitecture artifacts. - Not force unjustified complexity into the microarchitecture nor the software. |
It’s worth remembering that the surviving CISC architectures (x86 and z/370) are less CISCy than VAX and 68k were, in terms of number of address operands and complexity of addressing modes. And ARM is not a classically RISCy RISC. Instruction sets seem to have converged on a pragmatic middle ground — except for RISCV :-)