[watersb]

I believe that modern x86 processors store decoded micro-ops in the I$ instruction cache.

I always understood micro-ops to be fixed length.

Sure, you have to decode the variable length instructions at some point. But that extra work, relative to aarch64, is in practice amortized over the lifetime of that cache line.

[mmaniac]

That's not how it works for either Intel or AMD's current designs. Both use an L1 I$ which consists of encoded instructions, while adding a small uop cache (sometimes called L0) for recently decoded instructions.[1][2]

Intel's Netburst architecture stored decoded instruction sequences in its L1 cache, which Intel called a trace cache.[3] This didn't work out too well, so Intel reverted to a conventional L1 cache with the successor Merom[4] and introduced the uop cache shortly after with Sandy Bridge[5].

[1]https://chipsandcheese.com/2021/12/02/popping-the-hood-on-go...

[2]https://chipsandcheese.com/2022/11/05/amds-zen-4-part-1-fron...

[3]https://chipsandcheese.com/2022/06/17/intels-netburst-failur...

[4]https://chipsandcheese.com/2023/02/05/intels-dunnington-core...

[5]https://chipsandcheese.com/2023/08/04/sandy-bridge-setting-i...