|
|
|
|
|
|
by JonChesterfield
815 days ago
|
|
|
It's a nice theory but I don't think it holds up. X64 executes from a micro op cache and there's no particular reason to expect the ops in that to be variable length encoded. Thus it only goes to the i-cache when that misses, at which point you've spent long enough digging around in the cache that the extra decoding probably doesn't matter. It's of like saying x64 is limited by only having 16 registers - there's only names for 16ish in the ISA, but there's loads more registers in the machine as part of hiding latency. |
|
|
Why not have just one, then?
After all, there's loads more registers in the machine as part of hiding latency.
The ISA either matters or it does not. Pick one.