[crote]

It all depends on your definition of "open", of course. As far as I know there is no open-source toolchain for any remotely-recent FPGA, so you're still stick with proprietary (paid?) tooling to actually modify it. You're pretty much out of luck if you need more than an iCE40 UP5k.

[snvzz]

>You're pretty much out of luck if you need more than an iCE40 UP5k.

Lattice ECP5 (which goes up to 85k LUT or so?) and Nexus have more than decent support.

Gowin FPGAs are supported via project apicula up to 20k LUT models. Some new models go above 200k LUT so there's hope there.

[robinsonb5]

Yeah I've used yosys / nextpnr on an ECP5-85 with great results - it's pretty mature and dependable now.

[bajsejohannes]

The up an coming GateMate seems interesting to me. They are leaning heavily on open source tooling.

chip: https://colognechip.com/programmable-logic/gatemate/ board: https://www.olimex.com/Products/FPGA/GateMate/GateMateA1-EVB...

[rwmj]

At least some Xilinx 7-series FPGAs have been reverse engineered: https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/...

[robinsonb5]

There's been some interesting recent work to get the QMTech Kintex7-325 board (among others) supported under yosys/nextpnr - https://github.com/openXC7 It works well enough now to build a RISC-V SoC capable of running Linux.