[formerly_proven]

Their process strategies lined up at final gen DUV and 1st gen EUV, but are divergent for the future: TSMC isn’t using high NA EUV for the time being and instead focuses on multi-patterning. Intel is instead trying to push high NA EUV into production first. We will see which works out; they can of course also both achieve success in different ways.

[aurareturn]

Given the recent history, it’s safer to bet that TSMC knows what they’re doing more. It feels like Intel is risking a lot to try to win back the crown. Hence, I believe in TSMC’s more.

[Detrytus]

Given the recent history TSMC is kind of repeating Intel's mistake here: they do not want to pay for new generation of the ASML litography machines (which are like $300M a piece), so they will leverage the last-gen ones and try multi-patterning instead. Didn't work for Intel last time, will end badly for TSMC this time.

[aurareturn]

That is a very simplistic look at it. We don’t know if TSMC has already done a lot of testing and thinks it can do it.

Meanwhile, Intel absolutely needed to try to take much bigger risks.

A pretty good article showing that low NA might be more cost effective: https://www.semianalysis.com/p/asml-dilemma-high-na-euv-is-w...

Lastly, the biggest chip you can make with low NA is 858 mm² which is nearly 2x bigger than high NA at 429 mm². This means it's impossible to make a chip as large as the Nvidia H100 GPU using high NA. If Nvidia uses Intel's 14A process, they will have to split the chip into multiple pieces and go chiplets approach. They're already doing it with Blackwell but that's stitching 2x 800mm²+ dies together. If they make a future chip using high NA nodes, they'd have to stitch 4x dies together to have the equivalent size which is considerably harder for GPUs.

I do believe that all highend chip makers will be switching to the chiplet approach. Everyone has to due to the high NA reticle limit. But TSMC's approach allows designers to keep making chips twice the size until around 2030. That's a huge advantage.

[formerly_proven]

That seems to be the precedent for this exact situation - iirc both the slight Intel 14nm and the large Intel 10nm delays were due to getting multi-patterning working at scale.