[arcticbull]

Sorry, why do you say that the P4/Netburst microarchitecture doesn't compare badly to modern chips? Their performance was utter garbage (at the time, and now) which is why the Pentium M architecture (a Pentium III derivative) was used when they built out Core. AMD was spanking them at the time with the K8/Athlon 64 and the Athlon 64 X2.

A super long pipeline allows higher clock rates but it takes a giant dirt nap when branch prediction fails and when you have a cache miss. You end up having massive latencies in these cases.

Further, generally all else being equal a lower clock rate allows you to be more energy efficient.

[bcrl]

The worst part of the P4 was when it went off into la-la land for 4000 cycles of replay. Did you issue a locked instruction? 4000 cycle penalty. Use rep ; movs? 4000 cycle penalty. Some weird internal condition with a misaligned store? 4000 cycle penalty. One could optimize to improve performance in those cases, but the performance glass jaws on the P4 were all consuming.

[bee_rider]

Just in terms of power consumption they don’t compare badly. Performance, of course, no comparison, haha.

Agree that it had tons of problems. But branch prediction has gotten better, compilers have gotten better, etc. Maybe they could be handled now!

[smolder]

Anything salvageable from the architecture likely has been used again by this point.