Is there a resource you'd recommend that would help one understand what `marketing nm` means technically, and why it's a quantity that the industry uses "because it's clear to them"?
All it means is average transistor density went up. It's supposed to mean by 2x but, in practice, it doesn't even mean that really. i.e. "At the 2020 IEEE IEDM conference, TSMC reported their 5nm process had 1.84x higher density than their 7nm process." [2]
And there are a lot stuff in there besides transistors: contacts, metal traces, power routing, ...
And there's also the quality of the software that draws the transistors. (No one draws billions of transistors by hand) And to further complicate things, there are many good reasons to make your transistors larger than the minimize size, and in fact many are.
So, it vaguely means density went up and unfortunately there isn't a single resource that says how to measure it or what the limit is.
Come to think of it, It's kind of like Moore's Law (the topic of TFA) in that it used to have a definite meaning. But then the meaning sort of evolved over time into something else without society actually agreeing on what that "else" was.
It isn't complex at all. Take the average density (average of sram and logic), take the square root of that, and you have (barring a factor) the node.
The best way to understand the dimension is to look at the contacted gate pitchm2 pitchcell height,and take the square root. The pitches obviously make an area, the cell height sets the 'design' component. So you get a reasonably scaled number.
Putting it that way also clarifies technology. Why euv, to tighten contacted gate pitch. Why cobalt: to tighten up metal 2 pitch (without killing resistance). Why backside metal: lowers cell height. There is of course more to it, but it is a good way to coarsely understand
A good way to know if it is marketing is if someone talks about feature sizes instead of pitches. Patterning is done by pitch. For example, you don't do euv to make smaller features. You do it to make more complex layouts at tight pitch.
> contacted gate pitchm2 pitchcell height,and take the square root
I am having trouble parsing `pitchm2 pitchcell height`.
Assuming that you meant to use `*` and then HN's markdown assumed it was italics, and placing `×` where italics start and begin:
sqrt(pitch × m2 pitch × cell height)
Then I am left with the questions:
What are the units of pitch? Best guess: length units? (Based on: cell height having length units. `m2 pitch` being dimensionaless?
Why do the pitches "obviously make an area" then?
What are the units of metal to pitch? Best guess: dimensionless. (Based on the final units of the sqrt being repoted in length, and the cell height presumably having units of length).
What the units of cell height? Best guess: length units, based on what the variable is called.
And there are a lot stuff in there besides transistors: contacts, metal traces, power routing, ...
And there's also the quality of the software that draws the transistors. (No one draws billions of transistors by hand) And to further complicate things, there are many good reasons to make your transistors larger than the minimize size, and in fact many are.
So, it vaguely means density went up and unfortunately there isn't a single resource that says how to measure it or what the limit is.
Come to think of it, It's kind of like Moore's Law (the topic of TFA) in that it used to have a definite meaning. But then the meaning sort of evolved over time into something else without society actually agreeing on what that "else" was.
[2] https://fuse.wikichip.org/news/3398/tsmc-details-5-nm/