[zachbee]

The reason HBM "isn't deterministic" is because the memory controller sometimes stalls reads when doing a refresh operation. It's possible to pause refreshes [1] or schedule refreshes ahead of time to get HBM and DRAM to act deterministic.

To be fair, that's a huge hassle, and I have no clue what level of support commercial HBM controllers have for refresh pausing or manual refresh scheduling. It could very well be impossible to do in practice -- and regardless, their performance numbers speak for themselves :)

[1] https://memlab.ece.gatech.edu/papers/TACO_2014_1.pdf