[Dylan16807]

> Now you might ask, why PAM3 and not PAM4? With 4 levels you can transfer 2 bits, and that seems much easier to work with. Well, it's because we hate ourselves, and we hate you. That's why.

> For context, a GDDR6 channel uses 16 DQ (data) pins + 2 EDC (Error Detection/Correction) pins and 16 transfers for 256 data bits and 32 CRC bits transaction. GDDR6X (from my understanding) does the same thing, but since it's PAM4, it sends 2 bits per transfer with (I think) half the number of transfers.

GDDR6X did not transfer 2 bits at a time despite being PAM4, because they disallowed transitions between the lowest voltage and the highest voltage.

Because of that each group of 4 symbols has 139 easily-stackable sequences, so they went with 7b4S.

https://research.nvidia.com/publication/2022-04_saving-pam4-...

I couldn't tell you how each transaction is laid out.

[Lramseyer]

Oh, interesting! I remember hearing rumblings that PAM4 was kind of a pain in GDDR6X. This makes sense. I still stand by my claim about PAM3 though.