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by pjc50
842 days ago
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HDL when operating as an HDL doesn't convert things into for loops or procedures, it's specifying a configuration of gates or FPGA lookup tables. Crucially it doesn't contain any layout information, so additional phases of work are needed. There is some confusion because the hardware can also be simulated, in a fairly straightforward way - you just need to model all those delays and run an event based simulator. Then the existing HDLs like (System)Verilog contain actual programming language constructs that are just there for use in simulation and can't actually be replicated in hardware. |
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