The issue I was concerned about was dealing with high-density interconnect microvias. This PCB is 10-layers with a core of 4 layers of normal vias, and 3 layers of lasered microvias on each side. Someone has actually done the sand and scan method on this board you can view here: https://balika011.hu/switch/lite/
PCBs can warp to various amounts post reflow, which can cause all sorts of problems with parallelism between your PCB and sanding surface. You would also be able to mitigate this type of attack by filling vias with conductive epoxy and plating over them, which is a well established process option in PCB fabrication.
I expected scan-and-sand to be somewhat automated, but they're doing it by hand? Incredible!
Might another way to resolve issues with the PCB dishing be to photograph the layers at a fraction of a layer height? So that in that way you have a lot more slices to work with, and you can digitally "flatten" the PCB?
Making a machine to automagically remove a tiny bit of material and image the result over and over would be easy for me. The image processing to take the stack of 3D sequential images and automagically process them into a netlist is well beyond my programming capabilities. If anyone thinks they could do this, contact me.
Not gonna pretend I have the solution, but it sounds like most of the groundwork for that has been laid out in medical imagery already. CT scans, combined into volumes, identifying structures..
There are automated tools for generating a netlist from scanned IC layers (nm thick). They're proprietary trade secrets of course, but it's done all the time.
It doesn't seem like this problem requires anything crazy, just traditional computer vision, but of course the devil is in the details.