[Sparkyte]

Sorta, this is actually a CPU cache thing, ARM can do it efficiently not needing a lot of CPU cache to handle parrellel decoding. x86 requires more cache to do so. However more cache has its benefits not just in this task. Cache is also getting cheaper.

[api]

That still implies both more logic and more "hot" silicon, so decoding is higher overhead.

I recall reading about creating a subset of x86_64 that would be faster to decode, but this would effectively be a different architecture so at that point you might as well go to ARM64 or RISC-V.

I do know that if the instruction set decodes efficiently and is compact (to reduce memory bandwidth) it really doesn't matter much beyond that.

[snvzz]

>I do know that if the instruction set decodes efficiently and is compact (to reduce memory bandwidth) it really doesn't matter much beyond that.

RISC-V is also simple, and that's relative to ARM64, nevermind x86.

I.e. it is achieving highly competitive code density and instruction count despite being simpler.

[Sparkyte]

It doesn't matter though technology is ever evolving. More cache will eventually be the norm on chips. Wide lanes for threads too.

M1 has four times the bit width of an AMD Ryzen processor. Supposedly next generation of Ryzen processors the Zen 5 will have a wider bit width.