[jsheard]

The signaling requirements are way too tight for pluggable VRAM to ever be a thing. If anything we're headed in the other direction, with CPUs losing pluggable memory in order to achieve tighter timings like GPUs do, Apple is already doing it and Intel is set to follow.

https://www.tomshardware.com/news/intel-demos-meteor-lake-cp...

[sspiff]

Exactly. There's a reason these chips are always surrounding the processor (since the 2000s) and why we haven't seen GDDR based plugable memory modules.

For this same reason (timing precision) you see that soldered DDR5 memory often reaches way higher speeds than what's available in DIMM or SODIMM form.

[magicalhippo]

We're already half-way in a heterogeneous future, with chiplets[1] and mixed cores[2][3] etc. Could we expand this to memory, having some soldered (on-chip?) high-speed memory, and then slots for additional slower, yet faster then the alternatives, DIMMs?

Or would the cost of the extra complexity of the memory controller likely not be worth it ever?

[1]: https://www.anandtech.com/show/13560/amd-unveils-chiplet-des...

[2]: https://www.intel.com/content/www/us/en/gaming/resources/how...

[3]: https://en.wikipedia.org/wiki/ARM_big.LITTLE

[jsheard]

> Could we expand this to memory, having some soldered (on-chip?) high-speed memory, and then slots for additional slower, yet faster then the alternatives, DIMMs?

Intel's already doing that with Xeon Max, it has both onboard HBM and an outboard DDR5 interface. It can be configured to run entirely from HBM with no DDR5 installed at all, or use the HBM as a huge cache in front of the DDR5, or to map the HBM and DDR5 into different memory regions to let software decide how to use each. I don't think there's been any indication of that approach filtering down to consumer architectures though, Intel is talking about doing RAM-on-package there but without any outboard memory interface alongside it.

[wongarsu]

Obviously high-end consumer CPUs already have about 30MB of on-chip memory, with server CPUs reaching a solid 300MB. We just prefer to call it L2 and L3 cache. If we add more memory in a chiplet format I suspect mainstream CPUs would simply expose (or rather hide) it as L3 or L4 cache.

Most software isn't even NUMA aware, and would completely fail to take advantage of a tiered memory hierarchy if it was given the option. But if we make the fast memory a big cache and let the CPU worry about it it's a "cheap" win.

Though there is the Xeon Phi which has about 16GB of on-package memory that can either be configured as cache or as "scratchpad" memory. But of course that's not meant for general-purpose software

[dist-epoch]

> Obviously high-end consumer CPUs already have about 30MB of on-chip memory,

AMD 7950X3D, a desktop CPU, has 144 MB of L2+L3 cache memory on-chip.

[cyanydeez]

to do this, I assume they're gonna need to stop die shrinks and drastically improve yields.

the reason to separate all the components are to ensure high percentage of functional pieces

[SAI_Peregrinus]

Chiplets help with yield a lot.

[jsheard]

I'm looking forward to the performance, but not looking forward to higher capacity RAM being segmented off to overpriced "professional" SKUs like high VRAM capacity is on GPUs. Currently you can run up to 192GB RAM on a consumer CPU platform but I doubt RAM-on-package consumer parts will scale that high.

[sspiff]

Yeah manufacturers love this evolution because it means everyone who wants or needs high memory will be forced to buy for their projected memory needs throughout the live cycle of the product on day one, and the only place they can get it is at inflated prices from the vendor.

I wonder how they will do this in the workstation and server space, I don't really see how they can do away with socketed CPUs.

I wonder if we will go back to slotted CPUs, with a SOM style board with CPU and memory being plugged into a motherboard/chassis that's really just an I/O back plane. How will multi Cpu communication look then?

I guess we already have memory being pinned to a NUMA node and connecting to others via a vendor specific interconnect, so maybe it's not that strange and different from today.

[jsheard]

> I wonder how they will do this in the workstation and server space, I don't really see how they can do away with socketed CPUs.

I'm guessing the endgame will be consumer parts all being RAM-on-package with no external memory interface, and workstation/server parts will take a hybrid approach like Intel is already doing with the Xeon Max chips which have 64GB HBM on the package and an external DDR5 interface supporting terabytes of slower bulk memory.

[dist-epoch]

Almost nobody upgrades a socketed CPU.

Sockets still make sense because you can choose between 10 or so different CPUs for a particular socket format.

But with just in time manufacturing you can imagine ordering the CPU directly from the motherboard manufacturer which solders it in place.

[ChoGGi]

I haven't upgraded this CPU yet, as it's still too new, but my last motherboard got two new CPUs, and previous was 2-3? (Maybe more it was awhile ago, thanks AMD)

[Liftyee]

> Almost nobody upgrades a socketed CPU.

Given that AMD has been releasing AM4 CPUs since 2016, I think it's reasonable to assume that many of those who know how to build computers in the first place have upgraded their CPU. Why switch the whole motherboard/CPU combination when you can just plug in a better CPU?

[bonton89]

Well, if you've been using Intel platforms you do because Intel obsoletes the chipsets at a rapid pace so there often isn't anything appreciably better to upgrade to on the platform.

[dist-epoch]

One could imagine a two deck PCB, where you have another PCB board underneath the main one for additional close memory chip locations with a high density vertical interconnect.