[drpixie]

And the intriguing load/store scheme.

There were no LOAD or STORE instructions. Instead there were "address" registers (18 bits wide), matched to each "operand" (60 bit data) register.

When you updated an address register, that memory address was automatically read into the correspond operand register. Except for the last couple address registers - updating them performed a write from the corresponding operand into memory.

By our current way of thinking, it seems arse about. But it worked well when you understood it, and apparently improved concurrency. Loads and stores became sort-of transparent. (Remembering that memory was as fast, sometimes faster than the CPU, so a few instructions saved was worth the occasional unnecessary load.)

See "Design of a Computer, The Control Data 6600" by J E Thornton.

[ithkuil]

An alternative way to model that in an ISA is the indirect addressing model coupled with the ability to use it when expressing operands in any instruction.

The models are isomorphic.

Write to an "address" register -> write to a register directly

Write to an "operand" register -> write to "(register)" (write to the memory at the address stored in the register)

Not sure which was the first architecture to model it that way. The PDP-11 had it.

You just need one bit in the instruction encoding to determine whether to use direct or indirect access. You need one bit in the instruction encoding if you have twice the registers.

You can save that bit if you make most instructions able to access the "operand" register only, and require that manipulation of the "address" register use special instructions.

In that case you have an "inverse load / store" architecture, where instead of using load store instructions to do indirect access you use them to do direct access.