[sylware]

RISC-V, being an ISA worldwide royalty free standard, is meant for assembly writting. The main reason, above the "comfort" reason of C and similar, was ISA abstraction which has no meaning in the RISC-V realm. The middle ground is those very high level language interpreters (python/lua/ruby/javascript/etc) written directly in RISC-V assembly (without abuse of any assembler preprocessor, ofc).

I am currently writting my own rv64 on x64 virtual machine process, to code my programs in rv64 and not anymore in x64 in order to be "real hardware ready".

BTW, anybody knows a EU based distributor of milk-v duo boards with the cv1800 SOC (the one without ARM cores and a rv64 MCU) which I can contact using my domestic email server?