[bgnn]

Chip design software GUIs are known to be unintuitive and unfriendly. I'm using them daily and it's in the way all the time. So I don't know what changed after these but I'm not seeing it as a user.

Oh, also, when will we get version control support? It's 2023 an no chip design SW has this.

[RicoElectrico]

I am scratching my head as to why Cadence Virtuoso is de-facto standard in custom analog design. Barely anyone uses Synopsys Custom Compiler. Having worked at SNPS I prefer schematic entry features of CC. Probing is more efficient, adding stubs to instances as well, lot of QoL stuff like these dynamic alignment guides, and finally most tool options are not hidden under F3 (as in Virtuoso) and show on the toolbar instead. Now I work at a small company which uses Virtuoso and have to re-learn a lot of stuff even if keybinds are 95% the same. I don't know how ADE compares to PrimeWave (formerly SAE), as we at Synopsys did not dogfood it and used custom text-based DSLs for all simulations instead.

[bgnn]

There is literally no good reason other than it being the standard I think. Analog design engineers are very averse to change. Everone learned the quirks of Virtuoso by now and nobody dares to try something else because they are not so much better at the end.