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by crote 875 days ago
> at some point I expect to finally see the "blending" of analog/digital chips that allow for a wide range of voltages

The irony is that the developments which made dirt-cheap MCUs possible have at the same time basically ruled this out.

Digital logic is almost trivial to scale down. With Moore's Law the compute core itself is indeed becoming basically free. However, IO does not scale down: modern chips have far fewer analog pins, far lower current limits, lower voltages, and are increasingly sensitive to ESD & over-voltage events.

An ATmega32u4 from 2008 is designed to operate on 5V, can handle 40mA per pin, and has 13 analog pins. It's rather sturdy and can take quite a beating. On the other hand, the RP2040 from 2022 runs on 1.1V, although IO is 3.3V. It can only handle 12mA per pin, which a chip total of 50mA. It has only 4 analog pins, which lack a lot of protection present on the digital pins. Basically, you'll damage it if you look at it funny.

I think it's best summarized by a somewhat-recent change in the USB 2.0 specification: originally the data pins were supposed to handle a 24-hour short to 5V without any issues. This requirement was dropped because such a short is incredibly rare in practice, and dropping that single requirement led to 16% reduction in silicon area for the transceiver and a 3x standby power reduction.

In today's world of ever-shrinking transistors, dealing with (relatively) high voltages and analog voltages is getting more and more expensive.

2 comments

I don't disagree at all, this analysis is spot on. The size of discretes on silicon has not shrunk nearly as much as it has for transistors. However, where I am coming from is that because the transistors have shrunk so dramatically it becomes possible to put an entire CPU in the "left over" space after you've placed the discretes.

There was a talk at either Hot Chips or ISSC in 2011? about a mixed mode chip where the die was 2/3rds analog parts and 1/3 digital part. Xilinx, the FPGA maker, came out with the "RF SOC" which has a "huge" analog section with multiple high speed ADCs and DACs and analog reference logic, plus and FPGA fabric, plus a quad-core AARch64 CPU. As I recall Cypress had something similar but the part family is escaping me at the moment.

But I am still looking for chip that integrates an SMPS so that they can run on a very wide range of voltages like the CD4000 series did (and still does). Combined with the ability to source 10's of milliamps like the ATMega and PIC chips did (and still do).

Plenty of chips integrate a voltage regulator so you can run digital logic from as much as 300 volts. Used in the controllers for some dimmable AC Led's for example.

I believe the linear regulator is implemented as a large resistor followed by some zener diode or something. I assume that's so the high voltage doesn't need to touch the silicon, merely the other end of some not-very-good insulator put on top.

The Cypress part family you are likely thinking of is the PSoC line, it’s a MCU mixed with very configurable analog front end.
Yeah that was what I was looking for, apparently it has an Infineon[1] part number now : https://www.infineon.com/cms/en/product/microcontroller/32-b... which is kind of cool.

[1] Apparently Infineon closed their acquisition of Cypress in 2020.

Made me realize that IO is the fundamental bits-atoms interface, thank you for writing.