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by thebruce87m
878 days ago
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> The degradation increases the amount of negative charge in the cell over time due to trapped electrons in the oxide and negates some of the control gate voltage, this over time also makes erasing the cell slower, so to maintain the performance and reliability of the NAND chip, the cell must be retired from use. https://en.m.wikipedia.org/wiki/Flash_memory IIRC from when I worked making microcontrollers, there is a feedback loop on the erase that makes sure the bits all read 1 as they should. This takes longer based on how many write/erase cycles have occurred. I’d have loved to find an actual data sheet to show you as an example, but here is something I found: https://e2e.ti.com/support/microcontrollers/arm-based-microc... > The erase time is worst case for a single sector when doing sector erase, or the whole bank if doing bank erase. In bank erase all the sectors are being erased at the same time so the time of the bank erase is equal to the time to erase the slowest sector. > Erase time degrades with the number of write erase cycles. Sometimes during erase traps (an extra electron or hole stuck in the oxide lattice) are formed in the erase oxide. These traps make the next erase harder. Some of the traps will anneal with time and high temperature. |
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