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by acje 874 days ago
I don’t think SMT makes much sense if you have enough cores to more than max out the power envelope of the socket when they all run at max frequency. You can then dynamically tune the system to get as close to the power envelope as possible with the available threads by adjusting the power usage of each core. Also the cores would be simpler. Meaning more power efficient and potentially eliminate some attack vectors as mentioned earlier in this thread.
2 comments

Yeah, I've been surprised that hyperthreading was still around for quite a while now. It's from an era when the goal was to squeeze as many instructions per time unit as possible through a given transistor count. Or perhaps more correctly, through a given chip area. But that's in the past, now the goal is achieving as many instructions as possible per watt. And if that requires a larger chip (or even better: more chiplets), so be it.

I think two cores that are 50% utilized burn through less power than one core that is 100% utilized but that also contains all the extra stuff it needs to pretend it's two cores. And that's the best case scenario. Quite possible that in the days HT was introduced, idle units weren't half as good at not consuming power as they are now.

It's just anecdotal but I really feel like Intel hyper threading helped their cores not pipeline stall more than anything so it may have helped the feel and benchmarks until their core count rose or their thread scheduler improved.
> max frequency

There is no such thing, basically core speed is a curve where they get more and more inefficient the faster they run, and the hard frequency limit is just some arbitrary point on that curve.

If a particular HT friendly workload gets more done at a specific clockspeed, that is a significant boost to efficiency even if it uses more power, as clockspeed power usage scales very non linearly towards the top.

That being said, I dont think you are wrong. In consumer devices, HT seems like a bad tradeoff for a bigger, more cache heavy core.