[adgjlsfhk1]

the compilers work (produce valid code), but things like chip specific instruction cost models, full support for vector operations, and stuff like that are nowhere near where they are for x86 or M1 (because there are way less users and developers to make sure the codegen is optimal)

[FullyFunctional]

[citation needed] Do you have anything concrete to support "nowhere near where they are for x86 or M1"? I literally eyeball RISC-V code all day long for a living and it's not like there a massive performance lost to the compiler.

[brucehoult]

Core-specific cost models are a bad idea when you have a large variety of cores in use. Auto-vectorisation doesn't work well on anything, except in the most trivial cases, and none of the popular boards [1] yet have the official RISC-V vector ISA anyway -- that will change this year, hopefully.

[1] there is now in the last month or two one (1) board with RVV 1.0 but it's only single core vs the quad core in popular boards, and also has only 512 MB of RAM vs 4 / 8 / 16 GB on the popular boards (and 128 GB on the Pioneer).