I’m not deeply familiar with either, though I have written a toy x86_64 bootloader once. There are more levels in x86_64 (which makes sense to me that a larger address space would benefit from a sparser encoding). What else is significantly different?
x86 in some modes (PSE but not PAE) has 4MB superpages, whereas in PAE mode or in x86_64 they're 2MB (first level). That's the only one I remember off-hand.
There are also 1 GiB pages in long mode, but support depends on the processor and CPUID's output. Almost all modern x86 processors in the last several years should have it, I think.
Some also technically support it, but it doesn't gain you a whole lot as the TLB will split it down to a 2MB TLB entry. Could save a bit of L2 for the page table entries under the right conditions, but you've already lost if invoking your page walk hardware is in your fast path to begin with.