[bradfa]

Generally high speed serdes IO blocks, which are needed for PCIe, in ASIC design are rather high power consumers. Even on Intel and AMD laptop spec CPUs there's generally many fewer PCIe lanes than on their desktop counterparts. The silicon space needed is also not small and sometimes the silicon process for making good low power but high performance serdes transceivers is not the best process for making the other things needed on the SOC, which can be solved with chiplet style designs but then you have another problem.

Most inexpensive and small SOC just can't justify adding such costs and complexities given that it's very likely their target volume buyer doesn't need such features.

I suspect this RISC-V SOC is priced in the $10-20 range, but I have no true understanding of the cost of this part. In that price range for SOCs almost no one has 4 PCIe lanes on offer, but some do have 1 or 2.