[kramerger]

> we didn't "tape out" our CPUs until we'd hit our testing plan which was defined by coverage metrics.

Just because you reached the same coverage it doesn't mean your are doing the same thing or that you were equally efficient in reaching it.

Beside, as any tester can tell you coverage is not a fool-proof metric.

[RealiZM]

Coverage in hardware is different from coverage in software. Solid part of System Verilog deals with that plus part of UVM. Plus coverage from simulation and property checking (aka formal) can be used together.