More of a parallel universe that didn’t work out caused by the same VLSI revolution.
It is what you get if you think computers need to advance by going parallel, meaning making it far easier to build whole systems out of lots of CPUs arranged in application specific topologies, and taking advantage of VLSI to put all the hardware on one chip to do it. The inspired part was using CSP as the formalism to define how this should work, which is where things like the channels in golang ultimately come from. The transputer has microcoded instructions for interprocess and interprocessor channel i/o.
It happened to walk straight into the RISC revolution, which it definitely is not part of, and so the only commercially successful spin off of it was their formally proven floating point unit which ended up licensed to Sun (and others iirc).
> More of a parallel universe that didn’t work out
Neuromorphic chips are built essentially the same way. The individual compute units are dog slow and only have tiny scratchpad memories (just like the elementary "SoC's" of a transputer), but you can etch many more of them on any given piece of silicon and they sip power compared to a standard CPU or even GPU, so the total amount of compute is significantly increased.
Neuromorphic chips tend to be SIMD (or effectively so) which is not the case with transputers, which were also not intended to be slow CPUs when they were introduced! With transputers it was up to the PCB designer to choose the topology of the links between nodes, and they were very fast for the time.
AFAIK no one ever put multiple transputers in an array in one package because it exposes one of the key flaws of the idea which is if you arrange them in a pipeline but only one of them has a flaw the whole thing is broken. That is a huge part of why the GPU style design has won for massive parallelism.
Xmos [0] still exists which, whilst not the same as the Transputer, does fabricate MCUs with hardware parallelism and a variant of C called xC with CSP primitives.
Graphcore is a direct descendent as well. That's message passing with different tooling - easy-ish to use from machine learning frameworks, deeply confusing to program directly.
No and yes. The idea of a SoC is pretty generic and existed in the industry at the time. But the Inmos team had an interesting mix of system and chip designers (some people who designed both) which led to an elevated interest in trying to get more functionality on-chip. E.g. the PLL clock generator, memory controller, on-board serial I/O. The idea that you could sell a custom chip with CPU and some application-specific peripherals onboard also existed. Inmos developed a disk controller transputer (M212) to showcase that concept.
It is what you get if you think computers need to advance by going parallel, meaning making it far easier to build whole systems out of lots of CPUs arranged in application specific topologies, and taking advantage of VLSI to put all the hardware on one chip to do it. The inspired part was using CSP as the formalism to define how this should work, which is where things like the channels in golang ultimately come from. The transputer has microcoded instructions for interprocess and interprocessor channel i/o.
It happened to walk straight into the RISC revolution, which it definitely is not part of, and so the only commercially successful spin off of it was their formally proven floating point unit which ended up licensed to Sun (and others iirc).