[bob1029]

I spent an entire summer circa 2010 trying to rip the decrypted DSD signal off an SACD player via an FPGA. I figured the simple on/off levels would be easy to grab but I had not much success beyond being able to visualize it on a scope. Was trying to get at the high resolution, multichannel tracks for a Lord of the Rings soundtrack.

[dfox]

I spent somewhat inordinate amount of time around 2010 by designing a Class D PA amplifier that used DSD-like bitstream internally. The idea was to convert analog input signal into this bitstream by what amounted to somewhat convoluted sigma-delta ADC, process that with FIR filter in digital hardware and drive MOSFET H-bridge with that. The thing ended up ridiculously complicated (with somewhat impressive amount of SRAMs) and totally non-practical (through hole 74HCT and GALs, which worked out to something like 15 3U eurocards). I never got to complete the board layouts, much less building it, which is probably a good thing.

[amluto]

As I understand it, the really nice modern class D amplifiers use feedback internally, which more or less eliminates using a pre-computed DSD-like bitstream as a good option.

On the other hand, FPGAs and really fast microcontrollers are a thing now, so you could probably get a chip with a nice internal ADC, digitize the output voltage, and use an actual computer program to drive the H bridges, thus making an extremely non-cost-effective class D amplifier :)

[dfox]

The “high-end” PA Class D amplifiers (the kind of thing that is used in clubs on Ibiza and such things) have feedback loop and the feedback loop is closed in purely analog domain around the whole Class D amplifier, alternatively one can look at that as an giant SMPS with large slew rate, which is what that is (there is a bunch of anecdotal evidence around the losses in the output reconstruction/low-pass filters that apparently can reach temperatures that the solder melts, which is kind of problematic when in the chassis the board is mounted components down).

Issue with doing what I tried to do and FPGAs is that the overall architecture of this kind of DSP is perfect example of a thing that does not match the FPGA architecture. It boils down to ridiculously long shift register, few bits per tap of parameter data and reducing tree for the result, ie. most of that is ridiculous amount of 1bit SRAM cells.

And well, in the end I realized that idea, in not-even-that-fast-for-the-time ARM11TDMI and software and 24b samples at 96kSps (both of which is realistically a total overkill for this application), but without the DSD input (in theory the code that produced the output can be inverted and used to convert DSD to some sane representation, but well, I did not really care)