[schmidtleonard]

> Modern, high end FPGAs have a feature known as Raw SerDes

That's like saying "did you know that advanced microprocessors have the capability to bypass I2C and output voltages directly on the pins?!?!?!?"

First of all, it's backwards. The physical layer comes before the protocols and is always there at the base. Second of all, the world does not exclusively run on I2C. Some people want SPI busses or to toggle transistors with GPIO. That's fine. Sure, gate it behind different permissions, but don't just rant at what you don't understand.

If you want a concrete example where serdes access is important, look up JESD204b, but in general there are loads of real-time systems or bespoke processing applications where it makes sense to dispense with the complex and temperamental packet-switched infrastructure in places where that complexity and nondeterministic behavior is likely to cause more trouble than good. There are also applications to backplane connections (if you are encapsulating PCIe, you want to run slightly faster than the PCIe so the PCIe can run at full bandwidth), even to the development of next-gen PCIe itself. It's not magic, it is not delivered by a stork, it needs to be prototyped, and that's another thing FPGAs are used for.