[xw3089]

There are tons of other practical problems. The HLS generated verilog is name mangled. This makes it really hard to generate all the various control files you need to run the EDA flow, the software that assists in turning verilog into manufacturing files. If you have a super stable design, like a codec, then you can deal with it because it’s basically a waterfall development cycle. But if you have a design whose requirements are changing as you develop it, like most things. HLS doesn’t fit into the existing organizational structures and you’ll end up with a less optimal circuit.

[Dolu]

> The HLS generated verilog is name mangled

Chisel, SpinalHDL, Clash, Migen, Amaranth aren't HLS

Most of the time, if you get some verilog out of those tools with mangled names, it can be because of bad coding practice.

Here is some examples about how to preserve good names for SpinalHDL : https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/S...

[tverbeure]

This is not true for SpinalHDL and Amaranth/migen (I can’t speak about Chisel): the names of registers and IO ports are totally predictable and there’s no issues generation timing constraints, placement constraints etc.

If our backend team doesn’t complain about HLS, it most certainly won’t complain about RTL generators.

FWIW: the codecs are not super stable designs at all. They’re under constant development.

For modern ASICs, layout partitions are so large that your backend tools see hundreds of thousands of instances that are on the same clocks. The synthesis tools may have special recipes for optimization (which, again, you can still do), but the backend flow is mostly concerned with meeting timing on that clock. Except for external IOs, it’s rare to have specialty timing constraints at within partitions.