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by xw3089
900 days ago
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I think this comes from the idea that running the EDA flow is like compiling software and that’s the problem, it’s not. The EDA flow, the software that goes from verilog to manufacturable files, is electrical engineering. Sure, it’s heavily automated, but it’s not fully automated. And if you want a semi decent chip, the tools need a ton of hand holding. And if you want a great chip, get prepared to dig into all the intermediate files… If you just want a chip, any chip, they can kinda give you that in a fully automated way. |
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