| > the LVDC actually contains triply-redundant logic I didn't know that was just for the LVDC. > emulate this voting scheme with 3x microcontrollers with a 4th to tally votes will not make the system any more reliable I think that's clear enough; the vote-tallier becomes a SPOF. I'm not sure how Tandem and Stratus handled discrepancies between their (twin) processors. Stratus used a pair of OTC 68K processors, which doesn't seem to mean voting; I can't see how you'd resolve a disagreement between just two voters. I can't see how you make a voting-based "reliable" processor from OTC CPU chips; I imagine it would require each CPU to observe the outputs of the other two, and tell itself to stop voting if it loses a ballot. Which sounds to me like custom CPU hardware. Any external hardware for comparing votes, telling a CPU to stop voting, and routing the vote-winning output, amounts to a vote-tallier, which is a SPOF. You could have three vote-talliers, checking up on one-another; but then you'd need a vote-tallier-tallier. It's turtles from then on down. In general, having multiple CPUs voting as a way of improving reliability seems fraught, because it increases complexity, which reduces reliability. Maybe making reliable processors amounts to just making processors that you can rely on. |
Tell them both to run the calculation again, perhaps?