[SilverBirch]

You had me in the first half. You're absolutely right about the shortcomings of Verilog. I see a lot of similarities between it and PHP - where the language has developed features it doesn't really understand and therefore hasn't quite got right. But it has developed. It goes a fair way to let you do things that otherwise you have to generate code for. And everyone rolls their own code gen. VHDL is vastly inferior at this point in terms of its capabilities especiallly in the verification space, and where Verilog loses in terms of Loose typing it can ameliorated with linting.

[gsmecher]

The "language wars" narrative feels pretty played-out, so I'm not going to get drawn into it. In the software world everyone seems to recognize that different languages have different strengths, and that there's room for more than one. I'd love to play to the strengths of each language (example: SystemVerilog for verification; VHDL for fixed-point DSP).

A polyglot HDL world is elusive because simulator vendors insist on charging incrementally for language support, and open-source tools fall into either camp Verilog or camp VHDL. This is just another thing to lament.