[ahmetak]

Actually thats why we need an AI to generate Verilog / VHDL from images of tomography so it can be testable part by part or whole on a FPGA or simulation.

Many part of the chip is actually replication of same compenent or library like DRAM, ROM, Arithmetic operations so always there should be a pattern. Scanning should also work from low resolution to high resolution part by part to find pattern.

And also foundry is not as much as you think, most of the cost is R&D not the production.

https://www.granitefirm.com/blog/us/2023/04/29/cost-of-chip-... https://www.tomshardware.com/news/tsmc-reportedly-adds-advan...

"60-ish A100/H100 GPUs per wafer" and 7nm Waffer cost is $10k

[vineyardlabs]

Did you actually read the article you linked? 10k per wafer is the cost in-production, at scale. The tapeout process for a 7nm chip is 10s of millions of dollars before you even get to paying per wafer.

[ahmetak]

https://www.linkedin.com/pulse/talk-chip-design-tape-out-ver...

https://www.reddit.com/r/ECE/comments/7hjlpg/for_anyone_curi...

You are right for production, I was meaning for verification. MPW is around about 20-30k for 7nm.

In full production even with tapeout cost which is $15M for 7nm chipset cost $1500 per die after sell 10k. Best price for A100 is around $6k in monopoly now.

Even before production, after interpreting images, AI can also collect IP cores and produce new ones in the next steps.