[kuripyon]

Neat! I'll check it out tonight. HW division and mod are going to be difficult-ish: I was thinking that either I could use a DSP block or, failing that, bump up the clock frequency of the LUTs used for div/mod until the 16div16 operation can appear to occur in 3 main CPU cycles. I'd love to contribute whatever I can to the project - I mostly work with Lattice stuff but I guess it couldn't hurt to give Xilinx's tools a try^^ Thanks!

[sybreon]

Multi-cycle operations can actually be inserted into the pipeline. The `ena` signal would just need to be held low during that time.