What you're seeing there labelled LPDDR5 is the memory /controllers/, not the memory itself. The silicon area for the amount of DRAM we're talking about would dwarf the IC you're looking at -- and the 3 nm process that the logic is made on is not compatible with deep-well capacitors used for DRAM. There's a significant amount of SRAM on the chip (the SLC blocks, and many other cache blocks), but orders of magnitude less than the external DRAM we're discussing.
