[jeffbee]

What about something like https://github.com/abseil/abseil-cpp/blob/master/absl/string... ? ASCII lowercase can be something like

     auto is_upper= (x > '@') & (x < '[');
     return is_upper ? x+32 : x;

Which boils down to add, add, cmp, cmov on x86. It might save some cache traffic, but the cache traffic is less code since it's only a mov. The version that's code instead of lookups probably exacerbates register pressure problems in large programs? I don't have good intuition for which would be more efficient in practice.

[dragontamer]

Your 8-bit lookup can never be parellized, while the add/cmp/cmov is really easy AVX512 that probably auto-inlines and auto-vectorizes.

I dunno, it's ridiculously a benefit to the code by my instinct. While lookup table looks pretty bad.

[jeffbee]

> can never be parellized

I mean, I'm not skilled enough in those ISA extensions to stick my neck out. It's not totally obvious to me that there is not some shuffle or permute facility that can load 64 bytes at a time from LUTs.

[dragontamer]

> It's not totally obvious to me that there is not some shuffle or permute facility that can load 64 bytes at a time from LUTs.

You are talking about vgather and/or vscatter, which are well known to be very slow AVX2 or AVX512 instructions.

Maybe a future CPU will make these instructions high performance. But no modern 2023-era CPU has a high-speed vgather.

Like: the vgather does one-at-a-time slow. You basically lose parallelism even if the vgather instruction describes what you want to do, it's not an effective parallel operation today (and may never be)

--------

Pshufb as a 4-bit LUT is an exception and is effectively a high speed (but very very small) lookup table. Like every cycle 64 bytes at a time fast.

You are limited by the 16-byte lookup size (aka the size of an SSE register), maybe a bit bigger if there are new instructions I dunno about.

[gpderetta]

Vectorized gather loads can do just that. But currently are pretty underwhelming on x86 machines.

[gpderetta]

Although it can't be easily vectorized, it can be pipelined, that can help both hide the access latency and keep the lookup table hot. The code is not going to be pretty thorough.

[vardump]

> Which boils down to add, add, cmp, cmov on x86.

By using SIMD instructions like AVX2 you can do 32 characters in parallel. With AVX512, 64.

Pretty easy to write something way faster by not using a LUT.

[nwellnhof]

Yes, this is a good example where LUTs are very likely to be slower, especially if you can avoid branch mispredictions with cmov.

[tgv]

Except that in Unicode, this doesn't work.

[dragontamer]

The example code is a 256-byte lookup table, meaning the original example won't work with Unicode either.

In fact, I'm pretty sure that Unicode cannot be solved with a lookup table due to its variable length, but maybe you can prove me wrong? (Assuming UTF8 here)

[tgv]

256 is indeed pretty limited.

Unicode does have a limited space, but it cannot be stored practically in single table. It currently runs up to 0x323AF, a bit over 200k, and most of the characters of course don't have a lower/uppercase mapping. The implementations I've seen do a few comparisons and then delegate to a table.

But: horses for courses. If you have to normalize a lot of Latin-1 text (such transform case, or strip diacritics), you can probably write some vector instructions that runs circles around a simple LUT. But it's not going to be as easy.

[ilyt]

What the fuck you expect "bit reversal" to even do in unicode ?

[tgv]

I had the vague impression this was about lowercase. No need for expletives. Perhaps you should comment elsewhere.