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by Loq
988 days ago
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> loose specification of the RISC-V ISA. This is being worked on with the Sail model [1]. In order for a RISC-V extension to be ratified it ought to be implemented in Sail. The understanding is also that the RISC-V ISA manual should be built with code snippets from the Sail model (similar to how the Arm ARM is build from ASL definition). The main issue is a lack of people willing and able to write Sail for RISC-V. But that is beginning to change, since RISC-V member companies are increasingly use Sail. As an example, the RISC-V exception type is defined in [2]. Is that precise enough for you? The formal RISC-V ISA specification is not finished, you are welcome to make a PR to clarify things. [1] https://github.com/riscv/sail-riscv [2] https://github.com/riscv/sail-riscv/blob/master/model/riscv_... |
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