[AdamH12113]

I think there are too many steps with too many opportunities for failure and too little training data for such a thing to be feasible for the foreseeable future. Almost any small error of the kind that GPTs produce can prevent your board from working or destroy components. Picking the wrong part number or connecting the wrong pins is a hard fail that costs a fair bit of time and money to fix. Softer error like picking the wrong capacitor value for an RC filter or using bad trace routing would be tricky to debug.

Maybe a better approach would be to have an LLM generate RTL code for an FPGA.