[hunson_abadeer]

> if you go RISC-V, you are free to switch CPU providers.

That's not even true within the ARM ecosystem itself. The chips from Infineon are not source-code compatible with STM, STM is not compatible with Microchip, Microchip is not compatible with TI...

The problem is that the ARM core is just a portion of the architecture. Everything on top of that - GPIO, memory interfaces, timing, etc - is vendor specific, and will stay that way for RISC-V. RISC-V is just an instruction set architecture (with some appendages), not a blueprint for a complete CPU / MCU / SoC.

Not to mention, the chips also won't be electrically-compatible. Your hardware architecture can be as daunting to redesign as the code, if not more so. There's a reason why we try to do as much as possible in software, after all...

[snvzz]

>Everything on top of that - GPIO, memory interfaces, timing, etc - is vendor specific, and will stay that way for RISC-V.

Not as true for RISC-V, as there's efforts (some of them complete) to standardize interfaces to standard peripherals.

E.g. timers, gpios and watchdogs.