[joachimma]

Anyone have some insight into why RISC-V seems to be getting traction?

Has there not been prior attempts to make an open source cpu?

Is there a lot of skill in making the ISA? It seems to me (naively) that most talented EE students could probably come up with their own ISA, or is there some "magic" in the RISC-V one?

I assume that there are a reference implementations in VHDL/Verilog and Cadence and good support in compilers. Is this what pushed through, where others failed?

[brucehoult]

RISC-V is not an open source CPU, it is an open and license-free Instruction Set.

A number of open source RISC-V CPU core implementations do exist -- including the THead C910, currently the highest performance RISC-V CPU you can buy at retail, used in the quad core TH1520 chip (Sipeed Lichee Pi 4A, BeagleBoard Ahead, Milk-V Meles, Roma laptop) and 64 core SG2042 chip (Milk-V Pioneer, an as yet unnamed dual socket board from PerfXLab, others coming soon). But there is no requirement to make RISC-V core open source.

There have certainly been other attempts to create an open ISA or CPU, either from scratch or else relicensing a previously proprietary design.

The problems with them which caused the RISC-V guys to make something new rather than use something existing included:

- unsuitable license e.g. GPL

- 32 bit only (OpenRISC, SPARC)

- all the opcode space already used, no room for future extension

- poor code density or other ISA problems e.g. delay slots

A number of existing ISAs have been made more open since RISC-V was developed, including POWER and MIPS, but have been basically too late and also simply too restrictive and even not irrevocably open e.g. MIPSOPen which was not all that open and was re-closed after just six months (and MIPS make RISC-V now).

It's true that it's very easy to make up your own ISA, but it's hard to get it to be both good and also not similar enough to something else to get you sued.

And once you have your own ISA where does the software come from? Making or porting compilers and operating systems and everything is a task many orders of magnitude larger than designing an ISA or CPU core.

[spiralpolitik]

The big part is royalty-free open-source licenses. If you don't want to pay ARM for an ISA and RISC-V is good enough for your needs then RISC-V might be for you.

Plus there are limitations on which countries the latest ARM designs can be shipped to. RISC-V has no such limitation. The RISC-V Foundation is based in Switzerland and so isn't subject to US trade sanctions.

[panick21_]

> Anyone have some insight into why RISC-V seems to be getting traction?

Because its a a change in business model.

Its simple, in the past you had to pick a chip vendor and then make your software work on that. So you decide to get MIPS or ARM and then put your software on that.

RISC-V is different, you decide on RISC-V and you can start working on that. Then you can decide what vendor you want to get, or go with open source or do it yourself.

So in the past it was 'vendor -> isa', no its 'isa -> vendor'.

So bunch of guys in a big company lab can simply take an open source chip, throw it on an FPGA, develop the software and tell their manager "We can ship this, we just need to select a vendor for the actual chip". And then after 2 years if the vendor sucks, just switch vendor.

If you go to ARM. First there are lawyers and it can take months. Then once your software is on ARM, well now they have you by the balls.

RISC-V is free and vendors compete on an open playing field.

> Has there not been prior attempts to make an open source cpu?

As others have said, its not a CPU. Its an ISA specification. The RISC-V Foundation does not design chips.

As the other commenter has explained, there were other open ISA but they all had various technical and historical issues.

If you want actual open implementation of those specification, look at Chips Alliance, LowRisc or CORE-V for example.

> Is there a lot of skill in making the ISA?

Yes. Not for the base ISA, but if you want to have Crypto, Vectors, Atomics and so on and so on, its a huge effort. Yes some students designed the core, but RISC-V is far more then that by now.

But the real cost is actually that you have to port an insane amount of software, huge amount of man-hours to port everything and keep up with new extensions.

> I assume that there are a reference implementations in VHDL/Verilog and Cadence and good support in compilers. Is this what pushed through, where others failed?

There was just demand for something like it. Other efforts had historical issues or technical issues.

Once Berkley pushed it, even before the standard, various people started adopting it and it took of like a rocket after that.

[BirAdam]

ARM had some blunders with licensing changes for one, and then the split with ARM China was bad. Price plays a part. The next thing is that several open designs, including the reference design from Berkley, did very well at optimizing the most common instructions on which easily 90% of computation actually happens. As a result, very early RISC-V silicon showed seriously good performance at extremely low cost. As things are now, RISC-V is becoming increasingly competitive with ARM and x86 with amazing rapidity. There will be a few more hurdles in making RISC-V as performant as x86 or ARM, but given the ISA's open source nature, many eyes will make all bugs shallow.

[dkjaudyeqooe]

Because it's a free, well designed, clean and simple ISA.

[photonbeam]

Nvidia trying to purchase Arm got a lot of companies noticing that they have a sole-source provider, and instead want options

[askvictor]

ARM also license chip designs that implement the architecture. Not quite sure, but I think they'll do (for a fee) much of the process of making a chip that doesn't involve the fab.