[OhMeadhbh]

Yes. I saw that too. It turns out that "building a chip" is different than "building a chip that meets specfic requirements we got from the customer."

I'm not saying "building a RV32x is impossible," I'm saying there are people with existing tool-chains that favour Verilog or SystemVerilog (or even VHDL, though I don't know of them personally.) And telling them "no, you should use Scala / Chisel / Firrtl to model the features you want to add to the system in order to meet customer requirements" is kind of a hard sell for many customers.

[taway32r41]

I definitely agree with the primary point, "building a chip that meets specfic requirements we got from the customer" is not easy and is what matters.

However, RISCV cores abound. In pretty much any HDL known to man with varying design trade-offs and capabilities. It's extremely difficult to differentiate at the RTL level at this time. Not impossible, but it would be a significant investment, which is I guess SiFive's business model. Sell IP at prices cheaper than that.

Here is a high quality, well documented, SystemVerilog version intended for embedded applications that I know has been included in multiple ASIC and FPGA designs successfully.

https://github.com/lowRISC/ibex