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by robinsonb5
1026 days ago
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It always makes me grin when newbies complain that VHDL is too verbose. The pain of hooking up the Xilinx AXI interconnect in about three feet of (pre-system)verilog is something I will not forget in a hurry. Having wrapped it in VHDL with nice neat record types, I can now hook it up in just a few lines of VHDL. I think of it a bit like rat's nest wiring vs. nice neat labelled cable looms. |
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