[jacquesm]

There are a number of things that overlap here: the number of layers on circuit boards was still quite limited if you wanted the board to be affordable (2 layer boards were (back then...) 5x as cheap as 4 layer boards and 4 layers boards were 5x as cheap as 6 layer ones). There is the cost of the package itself and there is the cost of all of the infra around packaging and testing the die, the surface area of the chip die goes up with the square of the sides but the area available for interconnects only goes up with a factor of 4 unless you want to stagger your connecting pad. But that would complicate wire bonding.

Chip packaging has come a very long way from the days when a 40 pin DIP was considered a large chip. Kens (righto.com) has a series of articles about classic chips that show what high density designs looked like in those days and you can clearly see how the limits of packaging play into the designs of the dies themselves.

A 64 pin package that would not occupy a very large amount of board area (this is well before SMD became commonplace) would use all kinds of tricks such as staggered legs (sometimes up to three rows) and really tiny traces to be able to keep the costs down.

This is a fascinating bit of tech history and the fact that the packaging kept pace with Moore's law is maybe not quite as impressive as what was happening on the inside of the package but it was a major achievement and an enabler in and off itself.