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by jiggawatts
1043 days ago
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The variation is not smooth in real systems, but just like you’ve noticed: it’s right there in the L1->L2->L3->RAM->Disk hierarchy. Each one is physically bigger, further away, and higher latency. We might one day have 1 PB memory systems with 1 TB of on-chip cache… but the larger memory will still need more space and be further away… |
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