[kens]

To be superscalar, a processor must initiate multiple instructions per clock cycle. Having multiple functional units isn't sufficient to be superscalar if one instruction is dispatched at a time. You get higher performance from the multiple functional units since the next instruction isn't blocked while the previous one is executing.

According to "Modern Processor Design: Fundamentals of Superscalar Processors", the CDC 6600 was not superscalar because it had scalar instruction issue. This book says the IBM Advanced Computer system was the first superscalar design, but the project was canceled.

[Animats]

This is just a definitional issue. Older thinking was that having several instructions in progress at once was enough to be superscalar. Modern thinking seems to be that you have to initiate multiple instructions on the same clock cycle. Sources differ. Here's a good overview of the CDC 6600.[1]

Multiple execution units yes, multiple operations in progress yes, scoreboard yes, retirement unit no, branch prediction no, reordering no.

[1] https://people.eecs.berkeley.edu/~randy/Courses/CS252.S96/Le...

[kens]

Well, I can't stop you from using a nonstandard definition :-) The original definition of superscalar from Agerwala and Cocke of IBM was dispatching multiple instructions to the execution units every cycle. This is the same definition used by the other sources I've checked.

There are processors such as the Motorola 88100 and the Intel 80960KA that had multiple functional units and scoreboards, but were not considered superscalar. The follow-on 88110 and 80960CA processors could issue multiple instructions per clock, and were called superscalar by their creators. https://techmonitor.ai/technology/motorola_lifts_the_veil_on... https://ieeexplore.ieee.org/document/63681