[eesmith]

I enjoyed the economics answer and comment by Mark Booth:

> If generic floating point division were more important to modern CPU's then it might make sense to dedicate enough silicon area to make it single cycle, however most chip makers have obviously decided that they can make better use of that silicon by using those gates for other things. ..

> CPU manufacturers would only dedicate a large swath of silicon to a low latency floating point divide unit if they couldn't use that silicon more effectively to speed up the CPU in other ways. Generally speaking though, having more long latency FDIVs are a more efficient use of silicon than fewer shorter latency FDIVs

[not2b]

But you'd have to cram so many levels logic into that single cycle that you'd have to decrease the clock frequency to meet timing constraints, meaning that code that is not dominated by division would slow down. And a multi-cycle division can often happen in parallel with other operations.

[rcxdude]

If you simply try to take a design and make it take a single cycle while using the same area, yes. But usually you can trade off area (and power) for latency, by essentially having redundant logic throughout the operation. That's the point being made: the CPU manufacturers don't really consider it worth pushing this tradeoff (which is often quite non-linear).