| Ohh .. the ISA changed quite a bit between 2010 and May 2011! - 2010 opcodes left justified like MIPS, 2011 right justified and a func3 like modern RISC-V .. but rd on the far left, not between func3 and opcode. - register names in formats changed from xa, xb, xc (dst) to rs1, rs2, rd - 2010 lw uses xa for dst, sw uses xa for src like MIPS, ARM etc. 2011 has rd always in the same place, with sw using rs2 not rd, like modern RISC-V. - 2010 jalr has no offset, 2011 has 12 bit offset like now. - 2010 the literals for ANDI, ORI, XORI are zero-extended, 2011 unspecified (so I think all sign-ext) - 2010 j/jal have 27 bit offset (28 with shift?), 2011 25 bit field. - 2010 ADD/SUB/shifts have *W suffixes. 2011 is is like modern RV32. - 2010 has SRA / SRAI, 2011 only has logical. Possibly just a simplification for the lab. |