[littledanehren]

Note: This is my own opinion, and not that of my employer (Google) or based on trade secrets or other IP from my employer.

Keeping pre-erased blocks is useful, but it can only reduce the write latency to what the chip gives you. And the chip gives you a longer write latency than read latency, especially for MLC with smaller process sizes.

[ori_b]

True, there is a difference between read and write latency, but at least that is consistent and therefore easy to plan for. Large variance makes things far more difficult, in my opinion.

[mvgoogler]

It's actually not consistent. On MLC flash, individual write operations can vary by a factor of 6.

see: http://cmrr-star.ucsd.edu/starpapers/309-Grupp-1.pdf (PDF)