[hocuspocus]

> That has a large IGP for some reason? That doesn't make much sense, as you mind as well use the dGPU.

But maybe the goal is to finally offer an H class SoC that doesn't need a dGPU?

RDNA 3.5 with up to 40 CU should be well into Apple SoC Pro/Max territory.

[brucethemoose2]

But low power/idle efficiency will be awful using the desktop Zen 5 CCDs, if they are anything like the 7000 series.

They are optimized for high clocks, and the interconnect burns tons of power, especially with 2 CCDs (which reach into each other's L3 over the link).