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If anyone wants to dive a bit deeper into this, I always like to point towards: https://fpgaemu.readthedocs.io/en/latest/ If you're a software engineer interested in the hardware side of things, there's a great article for explaining the difference between the programming methodologies: https://nandland.com/lesson-7-what-every-software-programmer... To add some extra context, usually when a hardware designer is testing something on an FPGA they'll be testing just one specific IP core (a reusable unit of logic, cell, or integrated circuit layout design that is the intellectual property of the company). Let say, an Ethernet MAC for example. You don't necessarily need a chip like the one in the article to test that. You basically validate what all the inputs and outputs of said IP are going to be; you know that some signals are going to the PCS/PHY and some to a processing core/memory, and provided everything is done correctly then you should be able to slot the IP into your final chip design and everything works. That's not always the case though, which is why some companies end up have many stepping's (revisions of the semiconductor photomasks used to pattern an integrated cirucit). Many companies, my own included, make a business out of designing and selling these IPs to other companies without ever really knowing what the end customer wants to do with it. We just tell them what signals to put in, and what to expect out. With some of the larger FPGAs, you can connect many multiple IPs together and emulate the whole IC, but it depends on scale. You can easily emulate a whole Intel 4004 chip, but you're not fitting a whole Apple M1 design on a single device. With the chip in the article though, we're a step closer to that. Generally you might have 16+ FPGAs on a single PCB to test that scale of functionality. Even that's not a "true" test of a whole IC though, because of the delay in chip-to-chip communication. You might send your design to the foundry and find you've failed on timing. An Agilex 7 M-Series, one of the larger FPGAs in the Intel portfolio, has 3.9M LEs. This chip has what looks to be 18.5M. It's not a 1:1 comparison because they have different architectures, but you get a rough idea of the jump in scale here. This Versal Premium chip will be a massive boon to the likes of Apple, Tesla, NVIDIA, etcetera, because they can potentially emulate the entire chip function on a single die, meaning less steppings to get production quality silicon. |