[Taniwha]

This chip is for other chip designers - basically when doing chip design you want to make a product that works first time (or explain to your boss why he should spend hi 6 figures on a spin) - so you test test test ... what this is for is that a chip team will take their verilog design, compile it into luts and load it up here, it will likely run at ~10% of your designed speed - the alternative is compiling your verilog to code and have it run at 0.1% - 100x more testing