[8192kjshad09-]

This is super cool but I was left feeling like it missed the most important part, benchmarks. I know it mentions "2 clock cycles", but what does the latency for this end up being when you try to query it. I would be super interested to see how much faster this ends up being e2e.

[adam_walker]

Yes, benchmarks are missing. When I wrote this almost two years ago, I just wanted to explain the design at a high level to make it easier for people to understand the code. I didn't have access to a higher end FPGAs capable of 10G+ line rates to do any serious benchmarking, nor did I have access to precise Ethernet timestamping equipment.

However, I do have a bit of experience designing low latency FPGA based networking firmware. <100 nanoseconds measured wire to wire at the Ethernet level should be possible with 10G Ethernet. That's actually quite a long time on an FPGA. But, when you have latencies on the order of packet (de)serialization times, you need to be very careful about what you are measuring.

Also, I haven't actually built what I'm describing, so take my estimates with a grain of salt.